Selected Publications

Refereed Journal Publications:

• H. Hosseini and G. W. Dueck, “Toffoli Gate Implementation Using The Billiard Ball Model,” Multiple-Valued Logic and Soft Computing, Volume ??, Number ??, pp. 1-15, 2011. (to appear)

• R. Wille, D. Grosse, S. Frehse, G. W. Dueck, and R. Drechsler, “Debugging Reversible Circuits,” Integration, the VLSI Journal, Volume 44, Issue 1, January 2011, pp. 51-61
  

• D. Grosse, R. Wille, G. W. Dueck, and R. Drechsler, “Exact Synthesis of Elementary Quantum Gate Circuits,” Multiple-Valued Logic and Soft Computing, Volume 15, Number 4, pp. 283-301, 2009.
  

• D. Grosse, R. Wille, G. W. Dueck, and R. Drechsler, “Exact Multiple Control Toffoli Network Synthesis with SAT Techniques,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 28, Number 5, pp. 703-715, May 2009.

• D. Maslov, G. W. Dueck, D. M. Miller, and C. Negrevergne, “Quantum Circuit Simplification and Level Compaction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, March 2008, pp. 436-444.

• D. Maslov, G. W. Dueck, and D. M. Miller, “Techniques for the Synthesis of Reversible Toffoli Networks,” ACM Transactions on Design Automation of Electronic Systems, Vol. 12, Number 4, 2007, 28 pages.

• D. M. Miller, D. Maslov, and G. W. Dueck, "Synthesis of quantum multiple-valued circuits," Journal of Multiple-Valued Logic and Soft Computing, Vol. 12, Number 5-6, 2006, pp. 431-450.

• D. Maslov, G. W. Dueck, and D. M. Miller, "Toffoli Network Synthesis with Templates." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, issue 6, June 2005, pp. 807-817. pdf

• D. Maslov, G. W. Dueck, and D. M. Miller, "Synthesis of Fredkin-Toffoli Reversible Networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, issue 6, June 2005, pp. 765-769. pdf

• D. Maslov and G. W. Dueck "Reversible Cascades with Minimal Garbage," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, issue 11, Nov. 2004, pp. 1497-1509. pdf

• D. Maslov and G. W. Dueck "Improved Quantum Cost for n-bit Toffoli Gates," IEE Electronics Letters, vol. 39, issue 25, Dec. 2003, pp. 1790-1791. Corrected and expanded version: quant-ph/0403053.

• J. T. Butler, G. W. Dueck, S. Yanushkevich, and V. Shmerko, "On the numbers of generators for transeunt triangles," Discrete Applied Mathematics, Vol. 108, pp. 309-316, 2001.

• P. Wang, G. W. Dueck, and S. G. MacMillan} "Using simulated annealing to construct extremal graphs," Discrete Mathematics, Vol. 234, pp. 125-135, 2001.

• J. T. Butler, G. W. Dueck, V. Shmerko, and S. Yanushkevich, "Comments on Sympathy: Fast exact minimization of fixed polarity Reed-Muller expasion for symmetric functions," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, November 2000, pp. 1386-1388.

• W. MacCaull and G. W. Dueck, "Procedure for finding matrix models for substructural logics," Multiple-Valued Logic: an International Journal, Vol. 2, No. 4, pp. 305-321, 1997.

• G. W. Dueck and J. T. Butler, "A heat quench algorithm for the minimization of multiple-valued logic arrays," Computers & Electrical Engineering, Vol. 22, No. 2, pp. 103-107, 1996.

• P. Wang and G. W. Dueck, "An algorithm to find the upper bound of the distance between graphs," Journal of Combinatorial Mathematics and Combinatorial Computing, October 1995, pp. 81-96.

• G. W. Dueck and J. Jeffs, "A heuristic bandwidth reduction algorithm," Journal of Combinatorial Mathematics and Combinatorial Computing, June 1995, pp. 97-108.

• G. W. Dueck and J. T. Butler, "A minimization algorithm for nonconcurrent PLAs," International Journal of Electronics, vol. 73, no. 6, 1992, pp. 1113-1119.

Other Refereed Contributions

• Md. M. Rahman, G. W. Dueck, and A. Banerjee, “Optimization of Reversible Circuits using Reconfigured Templates,” 3rd Workshop on Reversible Computation, Ghent, Belgium, July 2011.
• Md. M. Rahman, A. Banerjee, G. W. Dueck, and A. Pathak, “Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit,” 41th International Symposium on Multiple-Valued Logic, Helsinki, Finland, May 2011
• Z. Hamza and G. W. Dueck, “Near-Optimal Ordering of ESOP Cubes for Toffoli Networks,” 2nd Workshop on Reversible Computation, Bremen, Germany, July 2010.
• Y. Sanaee and G. W. Dueck, “ESOP-based Toffoli Network Generation with Transformations,” 40th International Symposium on Multiple-Valued Logic, Barcelona, Spain, May 2010.
• H. Hosseini and G. W. Dueck, “Toffoli Gate Implementation using the Billiard Ball Model,” 40th International Symposium on Multiple-Valued Logic, Barcelona, Spain, May 2010.
• M. Soeken, R. Wille, G. W. Dueck, and R. Drechsler, “Window Optimization of Reversible and Quantum Circuits,” 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, Austria, April 2010
• S. Offermann, R. Wille, G. W. Dueck, and R. Drechsler, “Synthesizing Multiplier in Reversible Logic,” 13th IEEE International Symposium on Design and Diagnostics of Electronic
  Circuits and Systems, Vienna, Austria, April 2010.
• R. Herpers, G. W. Dueck, and N. Froebel, “International Distributed Computer Science Degree – Cooperative Education Efforts between Canada, Poland, Greece and Germany,” Informatics Education Europe IV, Freiburg, Germany, November 2009.
• Y. Sanaee and G. W. Dueck, “Generating Toffoli Networks from ESOP Expressions,” IEEE
  PacRim 09, Victoria, August 2009.
• D. M. Miller, R. Wille, and G. W. Dueck, “Synthesizing Reversible Circuits for Irreversible Functions,” 12th EUROMICRO Conference on Digital System Design, Patras, pp. 749-756,
  August 2009.
• R. Wille, D. Große, S. Frehse, G. W. Dueck, and R. Drechsler, “Debugging of Toffoli Networks,” Design, Automation and Test in Europe (DATE), pp. 1284-1289, Nice, April
  2009.
• R. Wille, D. Große, G. W. Dueck, and R. Drechsler, “Reversible Logic Synthesis with Output Permutation,” 22nd Conference on VLSI Design, New Delhi, India, Jan. 2009.

• R. Wille, D. Große, L. Teuber, G. W. Dueck, and R. Drechsler, “RevLib: An Online Resource for Reversible Functions and Reversible Circuits,” 38th International Symposium on Multiple-Valued Logic, Dallas, Texas, May 2008, pp. 220-225.

• R. Wille, H. M. Le, G. W. Dueck, and D. Große, “Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don’t Cares,” 38th International Symposium on Multiple-Valued Logic, Dallas, Texas, May 2008, pp. 214-219.

• N. Scott and G. W. Dueck, “Pairwise Decomposition of Toffoli Gates in a Quantum Circuit,” 18th Great Lakes Symposia on VLSI, Orlando, Florida, May 2008, pp. 231-236.

• R. Wille, H. M. Le, G. W. Dueck, and D. Große, “Quantified Synthesis of Reversible Logic,” DATE 08, Design, Automation and Test in Europe, Munich, Germany, March 2008, pp. 1015-1020.

• D. Grosse, X. Chen, G. W. Dueck and R. Drechsler, “Exact SAT-based Toffoli Network Synthesis,” 17th Great Lakes Symposia on VLSI, Stresa - Lago Maggiore, Italy, March 2007, pp. 96-101.

• D. Maslov and G. W. Dueck, “Level Compaction in Quantum Circuits,” IEEE World Congress on Computational Intelligence, Vancouver, Canada, July 2006. (D. Maslov, D. M. Miller, and G. W. Dueck, "Templates for Reversible Circuit Simplification," PACRIM, Victoria, Canada, 2005, pp. 609-612.

• D. Maslov, C. Young, M. Miller, and G. Dueck "Quantum Circuit Simplification Using Templates," DATE Conference, Munich, Germany, March 2005, pp. 1208-1213. pdf

• D. M. Miller, G. W. Dueck, and D. Maslov, "A Synthesis Method for MVL Reversible logic," International Symposium on Multiple-Valued Logic, Toronto, Canada, May 2004, pp. 74-80. pdf

• D. Maslov, G. W. Dueck, and D.M. Miller, "Fredkin/Toffoli Templates for Reversible Logic Synthesis," International Conference on Computer Aided Design (ICCAD), San Jose, CA, November 2003, pp. 256-261. pdf

• D. Maslov, G. W. Dueck, and D. M. Miller, "Simplification of Toffoli Networks via Templates," 16th Symposium on Integrated Circuits and System Design, Sao Paulo, Brazil, September 2003, pp. 53-58. pdf

• D. M. Miller, D. Maslov and G. W. Dueck, "A Transformation Based Algorithm for Reversible Logic Synthesis", Design Automation Conference (DAC), Anaheim, CA, June 2003, pp. 318-323. pdf

• G. W. Dueck and D. Maslov, "Reversible Function Synthesis with Minimum Garbage Outputs," 6th International Symposium on Representations and Methodology of Future Computing Technologies (RM), Trier, Germany, March 2003, pp. 154-161. pdf

• D. Maslov and G. W. Dueck, "Garbage in Reversible Designs of Multiple-Output Functions," 6th International Symposium on Representations and Methodology of Future Computing Technologies (RM), Trier, Germany, March 2003, pp. 162-170. pdf

• G. W.Dueck, D. Maslov, J. T. Butler, V. Shmerko, and S. Yanushkevich, "A Method to Find the Best Mixed Polarity Reed-Muller Expression Using Transeunt Triangle," 5th International Workshop on Applications of Reed-Muller Expansion in Circuit Design (RM), Starkville, MS, August 2001, pp. 82-93.

• S. Yanushkevich, J. T. Butler, G. W. Dueck, and V. Shmerko, "Experiments on FPRM Expressions for Partially Symmetric Logic Functions," 30th International Symposium on Multiple-Valued Logic, Portland, Oregon, May 2000, pp. 141-146.

• G. W. Dueck, M. Hu and B. Fraser, " A super switch algebra for quantum device based systems," 29th International Symposium on Multipl-Valued Logic, Freiburg, Germany, May 1999, pp. 118-124

• G. W. Dueck, G. Holowinski, K. Malecki, V. Shmerko and S. Yanushkevich, " Development of Zakrevskij's Minimization Strategy towards Arithmetical Polynomial Domain," Proceedings of 3rd International Workshop on boolean Problems, Freiberg, Germany, September 1998, pp. 101-108

• G. W. Dueck, C. Moraga, V. Shmerko and S. Yanushkevich," East - West Conferences as Scientific and Industrial Collaboration Strategies," Proceedings of International Workshop on European Scientific & Industrial Collaboration on Promoting Advanced Technologies in Manufacturing - WEIC'98, Girona, Spain, June 1998, pp. 427-433.

• B. Fraser and G. W. Dueck, "Multiple-valued logic minimization using universal literals and cost tables," Proceedings of the 28th International Symposium on Multiple-Valued Logic, Fukuoka, Japan, May 1998.

• V. Shmerko, G. W. Dueck, M. Perkowski, W. Rodgers, and S. Yanushkevich, "Bio-technologies in computing: the promises and the reality," International Conference on Computational Intelligence \& Multimedia Applications 1998, Monash University, Australia, February, 1998, pp. 396-408.

• M. Hu and G. W. Dueck, "A multiple-valued super switch algebra with applications to design of quantum device based systems," Fourth International Conference Applications of Computer Systems (ACS'97), Technical University of Szczecin, Poland, November 13-14, 1997, pp. 256-265.

• G. W. Dueck and W. MacCaull, "An efficient search for residuated algebras," Proceedings of the 15th International Conference of the Chilean Computer Science Society, Nov. 1995, pp. 170-174.

• P. Wang and G. W. Dueck, "On the families of extremal graphs without three-cycles and four-cycles," Congressus Numerantium, v. 106, September 1995, pp. 81-96.

• G. W. Dueck and J. T. Butler, "Multiple-valued logic operations with universal literals," Proceedings of the 24th International Symposium on Multiple-Valued Logic, May 1994, pp. 73-79.

• G. W. Dueck, "Direct cover minimization with cost-tables," Proceedings of the 22nd International Symposium on Multiple-Valued Logic, May 1992, pp. 58-65.

• G. W. Dueck, R. C. Earle, P. P. Tirumalai, and J. T. Butler, "Multiple-valued programmable logic array minimization by simulated annealing," Proceedings of the 22nd International Symposium on Multiple-Valued Logic, May 1992, Japan, pp. 66-74.

• G. W. Dueck and G. H. J. van Rees, "On the maximum number of implicants needed to cover a multiple-valued logic function using window literals," Proceedings of the 21st International Symposium on Multiple-Valued Logic, May 1991, pp. 280 - 286.

• G. W. Dueck and D. M. Miller, "RCM-MVL: A recursive consensus MVL minimization algorithm," Proceedings of the 20th International Symposium on Multiple-Valued Logic, May 1990, pp. 136 - 143.

• G. W. Dueck and D. M. Miller, "Directed search minimization of multiple-valued logic functions," Proceedings of the 18th International Symposium on Multiple-Valued Logic, May 1988, pp. 218 - 225.

• G. W. Dueck and D. M. Miller, "A direct cover MVL minimization using the truncated sum," Proceedings of the 17th International Symposium on Multiple-Valued Logic, May 1987, pp. 221 - 226.

• G. W. Dueck and D. M. Miller, "A 4-valued PLA using the modsum," Proceedings of the 16th International Symposium on Multiple-Valued Logic, May 1986, pp. 232-240.