Beatriz Iaderoza
  • M.Sc., 2003 - 2006.
    University of Victoria, Canada
  • degree, begin - end
    university, country


Research Topic: hardware/software co-design, FPGAs, hardware acceleration

Thesis Research:
Reconfigurable Co-Design of a Computationally Intensive Mathematical Problem
A reprogrammable hardware platform is used for the co-design and implementation of a computational intensive mathematical problem, namely the listing of irreducible polynomials over Galois fields of order 3 (GF(3)). The main goal is to accelerate the performance compared to an existing software implementation. This project uses hardware/software co-design methodologies and techniques, and it is designed, implemented and evaluated on two distinct platforms, not simply by simulations. FPGAs are used as part of the reconfigurable hardware in both a PCI-based environment and in a more successful System-on-Chip (SOC) platform, which takes advantage of the closely-coupled interconnection between the hardware and software, thus minimizing the communication overhead. The case study, findings and general analysis lead to a possible ideal architecture for future approaches. Moreover, a more general detailed strategy can be seen for the transformation from software to a co-design paradigm, maximizing parallelism.

Thesis Supervisor(s):
Micaela Serra and Ken Kent