Joshua Dick
  • MCS, 2003 - 2005
    University of New Brunswick, Canada
  • BCS, 1999 - 2003
    University of New Brunswick, Canada


Research Topic:
Hardware Acceleration of the Java Virtual Machine and Microsoft Common Language Runtime
Hardware implementation of neural networks
Embedded Systems
Reversible Logic


Thesis Research:
An Analysis of the Common Language Runtime for Hardware Implementation
Microsoft's .NET framework was developed to simplify development of Window's applications by consolidating many code management schemes into a single entity. At the heart of this platform is an execution environment known as the Common Language Runtime (CLR), which is a virtual machine. Virtual machines make for a second layer of abstraction between the executing application and the physical computer hardware. This makes virtual machines ideal candidates for hardware implementations, be it for performance gains, power consumption constraints, or portability to different computing domains. In order to take the software implementation of the CLR to a hardware implementation, an in depth analysis as to its executing behavior has to be performed in order to extract requirements for the subsequent hardware architecture. A mechanism exists to profile the executing CLR. This profiling API allows an application to hijack the executing code for profiling, as is done in this thesis. The analysis begins with an in depth study of the CLR instruction set architecture. Executing a benchmark and gathering data with regards to the instruction set will reveal its execution characteristics with respect to access patterns for data types, addressing modes and instruction encoding. The next step in the investigation analyzes the high level language support. The performance of executed instructions, method invocation, and the usage of classes are outlined. The final area of analysis is based on partitioning of the CLR into hardware and software components. A partitioning is proposed and the performance of the partitioning is analyzed by observing the data that needs to be passed between the partitions, counting the instructions that are executed in each partition, and the instructions that cause the switches between the software and hardware partitions. From this analysis a series of recommendations for a hardware implementation of the CLR are made, whether it is a full hardware implementation or a hardware/software co-designed implementation. These recommendations can then be taken into account when implementing a hardware CLR.

Thesis Supervisor(s):
Ken Kent